Phase locked loop (PLL) circuits are commonly used in integrated circuits, e.g., microprocessors, to provide clock signals to circuitry of the integrated circuit, for example to synchronize logic operations. A conventional PLL circuit consists primarily of a phase detector, a voltage controlled oscillator (VCO) and a power-of-2 frequency divider. A programmable frequency divider may be provided to enable the production of various frequency signals.
A base, or “oscillator” frequency is provided by the voltage controlled oscillator. Depending on a variety of factors, including, for example, a number of stages and an input voltage range, such a VCO can generate frequencies within a particular range, e.g., within an octave between 2.5 GHz and 5.0 GHz. The programmable frequency divider may be used to divide down the frequency of the VCO so that the output of the programmable frequency divider matches the frequency of the input (reference) clock signal.
The phase detector is used to compare the phase of the reference clock signal to the output of the programmable frequency divider to determine if the output clock is too fast or too slow. The phase detector generally outputs control signal(s) to control the VCO in order to slow down or speed up its oscillations so as to match the reference clock signal in both phase and frequency.
The power-of-2 frequency divider divides the VCO output by a power of 2, e.g., 2, 4, 8, etc., to provide a final output frequency. In many designs, this “power-of-2” is at least a factor of two because it is desirable to output a clock signal with a duty cycle very close to 50 percent. For example, many synchronous logic designs utilize both rising and falling edges of clock signals, and require minimum set-up and hold times from such edges. In general, the output of a VCO does not have a 50 percent duty cycle and dividing its output signal by a factor of two generally produces a clock signal with very close to a 50 percent duty cycle.
Unfortunately, this widely used conventional PLL implementation limits the clock signal output to a maximum of one half of the maximum frequency of the VCO. In many integrated circuits, e.g., microprocessors, it is generally desirable to utilize an accurate clock signal of a frequency that is greater than this limit.